Xilinx & BEEcube to Unveil Next-Generation FPGA-based Multi-core SoC Development Platform for Sun OpenSPARC
Xilinx, Inc. and BEEcube Inc. will jointly unveil a high-performance development environment for multi-core UltraSPARC CMT (chip multi-threaded) processors that reduces the time and effort required to design systems using the SPARC architecture. The companies will demonstrate the development system for the first time at this week's grand opening of an Advanced Research & Teaching Facility for Embedded System Design in Beijing, a joint venture between Beijing University of Technology (BJUT), the Chinese Ministry of Education (MOE) and Xilinx University Program (XUP),
The new BEEcube SoC development platform is built upon BEEcube's third-generation, large-scale multi-core processor BEE3 emulator and takes full advantage of the performance and flexibility of Xilinx' flagship Virtex-5 FPGAs. The platform enables researchers and hardware architects to quickly experiment with large scale, multi-core, multi-threaded FPGA implementations of UltraSPARC CMT processors for a broad set of end-markets including computing, industrial, scientific, medical, aerospace and defense, storage and networking.
Sun Microsystems' UltraSPARC T1 and UltraSPARC T2 microprocessors are the first 64-bit microprocessors available as an open source design and are freely available from the OpenSPARC website, http://www.beecube.com/opensparc.
"The newest emulation technology from BEEcube, powered by high performance Virtex-5 FPGAs, delivers a development platform that will be a great asset to designers who wish to evaluate the capabilities of the SPARC CMT architecture in a programmable device," said Patrick Lysaght, senior director for the Xilinx University Program and Xilinx Research Labs. "We're pleased that Xilinx technology is playing an important role in expanding the ecosystem for this important and popular open source processor core."
"This exciting collaboration between Xilinx, Sun, and BEEcube leverages our history of proven ASIC prototyping methodology from UC Berkeley and BEEcube, and brings it to the new world of multicore SoCs," said Robert Brodersen, professor emeritus at the University of California, Berkeley and chairman of BEEcube. "This new advance enables system architects using the SPARC CMT architecture to rapidly explore design trade-offs for cost/power/performance optimizations."
"The BEE3 hardware platform, based on Xilinx Virtex-5 FPGA technology, significantly expands the reach of Sun's Chip Multithreading SPARC architecture for the OpenSPARC community, which includes academics, researchers, and developers throughout the world," said Shrenik Mehta, senior director for front-end tools and OpenSPARC at Sun Microsystems. "The BEE3 platform provides users the ability to prototype and build significantly larger multi-core designs based on Sun's industry-leading CMT technology."
A single BEE3 module is capable of emulating either a quad-core 16-thread or two dual-core 8-thread UltraSPARC T1 processors, running on a binary-compatible OpenSolaris or Ubuntu Linux operating system. Each BEE3 module is designed using the latest Virtex-5 FPGAs. Existing users have a migration path from the Virtex-5 OpenSPARC single-FPGA Evaluation Platform to the new BEE3 quad-FPGA scalable computing platform. Altogether, the new BEEcube development system offers researchers and hardware architects six times more FPGA logic capacity, 64 times larger DRAM capacity, and support for PCI Express x8 and 10-Gigabit Ethernet interfaces.