Actel Enhances Performance and Reduces Power Constraints in Industry-Leading RTAX Space-Flight FPGAs
Actel Corporation, announced continued improvements in performance and usability of its industry-leading radiation-tolerant RTAX-S and RTAX-SL space-flight FPGAs, offering designers of space applications even greater advantages. Unburdened by the cost and schedule risks associated with radiation-hardened ASICs, the RTAX-S/SL family is the FPGA of choice for use in space-flight applications requiring built-in protection from radiation-induced single-event upset (SEU) events.
The enhancements to the RTAX-S/SL family of FPGAs include:
- Reduced static power consumption for RTAX-SL FPGAs of up to 80% compared to RTAX-S FPGAs. This saving in static power is particularly important for systems that go into stand-by mode and need to retain register and memory states while the spacecraft is running in battery mode (for example, while passing through the earth's shadow),
- A faster speed grade for the 4-million gate RTAX4000S FPGA, bringing 10% higher performance to the largest SEU-protected radiation-tolerant FPGA,
- A new, low-power RTAX4000SL FPGA, available in CQFP352 and CGA/LGA 1272 packages, reducing static power consumption by 50% compared to the RTAX4000S FPGA,
- New 624-pin CCGA and LGA packages for the RTAX250S/SL FPGA, giving designers a 17% increase in available I/Os and more than 50% savings in footprint. Devices are available today that are screened to MI- STD-883 Class B, Actel Extended flow, and Actel EV flow (which has processing steps identical to QML Class V) specifications,
- Increased absolute maximum junction temperature for the RTAX-S/SL FPGA to 135°C, giving designers an additional 10°C buffer to run the devices faster or at higher case temperatures.
About RTAX FPGAs
High performance and low power consumption, true single-chip form factor, and live-at-power-up operation all combine to make RTAX-S/SL the defacto FPGA platform for space designers. These devices offer high-performance at densities of up to 4 million equivalent system gates and 840 user I/Os. The RTAX-S/SL family features SEU-hardened flip-flops implemented without any user intervention, offering the radiation protection benefits of user-implemented triple module redundancy (TMR) without the associated overhead. RTAX-S/SL FPGAs offer much faster design cycle times than ASICs and eliminate the large up-front tooling charges and long fabrication cycle times associated with ASICs. Consequently, for typical low-volume space applications, RTAX FPGAs have lower cost of ownership and schedule risk than radiation-hardened ASICs.
For more information on RTAX-S/SL FPGAs: http://www.actel.com/products/milaero/rtaxs/default.aspx